| 摘要 |
PURPOSE:To eliminate the need for a carrier detecting circuit and to store an arithmetic result to a desired position, by interposing a logical circuit for compensation wherein binary-coded decimal numbers are corrected before an addend is inputted to an arithmetic unit and the address of a summed bits is indicated to a storage device. CONSTITUTION:A carry signal to the least significant digit bit among 8 bits, 8-bit addend, and 8-bit augend are inputted to the arithmetic logical unit ALU of a CPU constituting a microcomputer to obtain a carry signal to be outputted from the 8-bit signal of the sum of them and the least significant digit bit among the 8 bits. The compensating circuit 190 is provided between the ALU101 and a latch 107 connecting with buses 6 and 121 to which the 8-bit added is inputted. Then, binary-coded decimal numbers are compensated before the addend is applied to the ALU10 and the address of the summed bits is indicated to a data memory to eliminate the need for a carry detecting circuit, storing the arithmetic result at a desired position. |
