| 摘要 |
PURPOSE:To prevent an error due to the order of scanning, by charging a holding capacitor with an analog input signal continuously until right before a signal processor reads the charged value of the holding capacitor. CONSTITUTION:When initial-stage switches S11-Sn1 for relative addresses 1 in respective blocks are turned on, analog input signals e11-en1 charged in input capacitors C11-Cn1 are moved to holding capacitors C1-Cn. When the charging of the capacitors C1-Dn almost become stable, the output signal TPS1 of a timing circuit T1 goes down to 0 and the switch S11 is turned off by the output of an address decoder A1. The signal TBS1 goes up to 1 slightly later and the block switch S1 is held at 1 to read the charged value of the capacitor C1 in a signal processor SPU. Then, the signal TBS1 goes down to 0 and the switch S1 turns off. Then, the signal TBS1 goes up to 1 slightly later and the switch S11 turns on by the decoder A1. Similarly, the analog signals e11-en1 are read. |
