发明名称 PIPELINE CONTROL SYSTEM
摘要 PURPOSE:To detect out of synchronism between plural pipes, by inserting an abnormal data pattern into a stage in an empty state from a control pipe at the entrance of a controlled pipe, and checking the data pattern at the exit of the pipe. CONSTITUTION:A parity check is made at the entrance of the control pipe 301 and if information in the stage indicates significance, it is stored in a register for the parity check 304 by a signal 303. When it indicates insignificance, a parity error pattern is inserted. The parity check is made even at the exit 20 of the pipe 301; the information is stored in a register 504 when a signal 306 indicates the significance of the information or in a register 505 when not. When there is no out of synchronism between the pipes 301 and 302, a detection signal 507 shows 0. When out of synchronism occurs, the signal shows 1.
申请公布号 JPS58219646(A) 申请公布日期 1983.12.21
申请号 JP19820100706 申请日期 1982.06.14
申请人 HITACHI SEISAKUSHO KK 发明人 ISOBE TADAAKI
分类号 G06F9/38;(IPC1-7):06F9/38 主分类号 G06F9/38
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