发明名称 LOGICAL CIRCUIT
摘要 PURPOSE:To decrease the number of elements of a logical circuit with hysteresis, by connecting the base of a multicollector transistor (TR) to the collector of an input TR supplied with a constant current. CONSTITUTION:An input voltage VIN is applied to the base of a TRQ1 through a resistance R1, a constant current I0 is supplied to its collector, and the base of a multicollector type opposite-directional TRQ2 is connected to the collector. The 1st collector C1 of the TRQ2 is an output to a trailing-stage I<2>L logical circuit, the 2nd collector C2 is connected to the base of the TRQ1 through a resistance R2, and the emitters of the TRs Q1 and Q2 are both grounded. When the voltage VIN is lower than the base-emitter voltage V0 of the TRQ1 enough to turn on, the TRQ1 is cut off and the current I0 flows to the base of the TRQ2, so that the collectors C1 and C2 of the TRQ2 are both held at a low level. When the voltage VIN rises until VIN=V0X(R1+R2)/R2, the current I0 flows to the TRQ1 and the TRQ2 turns off to open the collectors C1 and C2. When the voltage VIN drops below V0, the TRQ2 turns on again and the collectors C1 and C2 are held at the low level.
申请公布号 JPS58218232(A) 申请公布日期 1983.12.19
申请号 JP19820100423 申请日期 1982.06.11
申请人 FUJITSU KK 发明人 TSUCHIYA CHIKARA;SANO YOSHIAKI
分类号 H03K19/091;H03K3/2893 主分类号 H03K19/091
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