| 摘要 |
PURPOSE:To reproduce a sampling clock having a stabilized and proper phase even when there is a disturbance in the initial stage of a clock run-in signal, by monitoring the amount of a phase shift by equalizing it. CONSTITUTION:An initial pulse generating circuit 34, a phase shift detection circuit 38, gate circuit 36 and counter 39 are provided. Over plural cycles of a clock run in signal, the amount of phase shift between the clock run-in signal and the output of 1/16 frequency divider 35 is equalized and monitored. After passing a fixed time, the preset timing of the frequency divider 35 is compensated by the output compensating pulse of a phase compensating pulse generating circuit 37 in accordance with the contents of the counter 39. |
