Interrupt coupling and monitoring system

摘要

An interrupt coupling scheme for a multiprocessor data processing network capable of providing the current status of all interrupts to all processors in the network employs an associated interrupt latch for each processor, to which the lines of the system data bus are bidirectionally coupled, and an address decoder that is coupled to the system address bus. When a processor wishes to interrupt another processor it drives the data bus so as to set the corresponding latch bit in the addressed processor's interrupt status latch, thereby presenting to the addressed processor an interrupt request signal. The contents of the interrupt request latch are selectively masked by the destination processor and then encoded into an interrupt vector to which the destination processor responds during its task assignment operations. When considered as a group, the interrupt status latches associated with the respective processors of the network effectively form an interrupt status table or matrix that is selectively addressable by any processor. The rows of the matrix correspond to the respective addresses of the processors for whom the interrupts are destined and the columns of the matrix correspond to the processors from which the interrupt requests originated.