| 摘要 |
PURPOSE:To speed up the addition of many bits, by inputting two input signals and a carry signal having different logic level from them, and connecting two kinds of full adders alternately outputting a summed signal and a carry signal having a different logic level from that of the input signal. CONSTITUTION:When input signals Ai, Bi and a carry signal Ci of the i-th digit are inputted to a type 1 full adder comprising an exclusive OR gate EXOR1, inverters IV2, 3, and tri-state inverters TIV4-7, the TIV4, 5 and 6, 7 are controlled on/off complementarily each other, and a sum signal Si of the signals Ai, Bi and a complement Ci+1' of a carry signal of the (i+1)-th digit are outputted. Further, when the signals Ai, Bi and Ci' are inputted to a type 2 full adder comprising an EXOR8, IV9-11 and TIV12-15, the sum signal Si and a carry signal Ci+1 are outputted. In constituting a multi-bit adder by alternately connecting the type 1 and the type 2 full adders, the path for the carry signal being a critical pulse is reduced remarkably, allowing to attain high speed addition. |
