| 摘要 |
PURPOSE:To obtain an amplifier circuit with less power consumption, by inputting a signal of the 1st and the 2nd input line to a gate of the 1st and the 2nd transistor(TR), respectively and transmitting each drain output to each output node of an FF. CONSTITUTION:An FF activating clock signal phi1 is applied to a source of load TRsQ2,Q3, and a source of switching TRsQ1,Q3 is both grounded. A signal of input lines 4,4' is inputted to a gate of TRsQ16,Q17, respectively, a drain output of the TRsQ16,Q17 is connected to output nodes 3,2 of the FF, respectively and a source of the Q16,Q17 is grounded, respectively. Further, the input lines 4,4' are grounded via TRsQ18,Q19 and an output of the FF is inputted to the gate of the Q18, Q19 from the nodes 3,2. When the input line 4 is at a higher potential than the line 4', the node 2 is a higher potential than that of the node 3, and when the difference exceeds a threshold value, charges on the node 9 are discharged, and a signal amplifying the potential difference between the input lines 4,4' is outputted. |
