发明名称 BREAKING TEST CIRCUIT
摘要 <p>PURPOSE:To compare the waveform of a voltage impressed on a switch with the period of a commercial frequency and to delay the maximum value of an envelope by a constitution wherein power sources having slightly different frequencies are connected to the opposite ends of the switch to be tested, respectively, and one end thereof is grounded by an auxiliary switch. CONSTITUTION:When the voltages between the opposite terminals of a switch 8 to be tested and ground are denoted as e1 and e2 and the phases thereof as phi1 and phi2, formulas 1 and 2 are given. Accordingly, an interpole voltage V is given by a formula 3. When omega1=2piX50 and omega2=2piX60 in this formula, the maximum value of an envelope is located at a time point of 50ms with the frequency thereof being 5Hz, and an oscillation of 55Hz is included therein. Accordingly, the waveform of the interpole voltage required for the breaking of a transmission line having a shunt reactor or the testing of a breaker of a grounded switch used for said breaking can be generated.</p>
申请公布号 JPS58211673(A) 申请公布日期 1983.12.09
申请号 JP19820094902 申请日期 1982.06.04
申请人 HITACHI SEISAKUSHO KK 发明人 TAKAHASHI ISAO;HIRASAWA KUNIO;OOSHITA YOUICHI
分类号 G01R31/327;G01R31/333;(IPC1-7):01R31/32 主分类号 G01R31/327
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