| 摘要 |
PURPOSE:To reduce deterioration of the performance in case of re-execution, by providing a delay designating bit of a re-execution cycle after correcting a 1 bit error, on a part of a microfield. CONSTITUTION:For instance, a 1 bit error is detected in an output of a micro- instruction register 22. In this case, execution of a present micro-instruction is halted, a correcting data is latched to the register 22 through a selecting circuit 24 from an error detecting and correcting circuit 23, and the processing is executed from the halted address. In this case, by AND of a delay designating bit D being a corrected register 22 output, and 1 cycle showing the start of re-execution, which is an FF 26 output, a micro-instruction cycle delay signal DEL is outputted to a clock controlling circuit 25. |
