| 摘要 |
PURPOSE:To reduce the number of wirings, by providing an address corresponding information input terminal on a memory LSI for transferring data to an MPU, and a peripheral control LSI, setting its terminal to ''1'' or ''0'', and transferring the address information through a data bus by the MPU in accordance with it. CONSTITUTION:LSIs 5-1-5-8 are connected to a microprocessor MPU through a control bus 2 and a data bus 3, and address corresponding information input terminals CA1-CA3 are provided on these LSIs 5-1-5-8, respectively. ''0'' or ''1'' is inputted to these input terminals CA1-CA3, as address corresponding information, and they are classified separately. Also, one selecting signal line 8 is connected to the processor MPU, and a selecting signal is sent out to all the LSIs 5-1-5-8. By this signal, a name data is inputted from the bus 3, and in accordance with its name data, the address information is transferred to each LSI 5-1-5-8 through the bus 2. Subsequently, coincidence of the address information is detected by a comparing circuit of each LSI 5-1-5-8, and the subsequent data is transferred. |
