发明名称 TEST SYSTEM OF ROM
摘要 PURPOSE:To facilitate an easy test of plural ROMs with small hard quantity, by providing a test address generating circuit, a horizontal parity calculating circuit, a horizontal parity deciding information storage circuit and a comparator respectively. CONSTITUTION:In the test operation modes of ROM1-1-1-n, a check address generating circuit 2 generates check addresses for test successively and feeds them to each ROM as well as to horizontal parity deciding information storage circuit 4. The output data of each ROM is supplied to a horizontal parity calculating circuit 5 for calculation of the horizontal parity. The horizontal parity is previously stored in the circuit 4 to the check address and compared with the calculated parity information to decide the correctness of reading. In such a way, it is possible to test plural ROMs with small hard quantity.
申请公布号 JPS58211398(A) 申请公布日期 1983.12.08
申请号 JP19820092807 申请日期 1982.05.31
申请人 FUJITSU KK 发明人 TAKAHASHI HIROSHI;OGAWA YOSHIHISA
分类号 G06F12/16;G06F11/10;G11C29/56 主分类号 G06F12/16
代理机构 代理人
主权项
地址