Serial-parallel signal converter - has address counter controlling serial inputting of digital data signals in matrix memory

摘要

The converter is for use with an LCD TV display has an address counter (11) counting clock pulse that regulate the inputting of the serial digital signal such that address signals (A1-A9) are generated. The address signals denote locations in a memory (13). The digital signals are entered serially into those of the storage locations described by the address signals. The outputting of the signals from the memory is such that all the locations are read simultaneously in parallel. The memory comprises a matrix of storage locations. An upper address decoder (15) decodes the higher valued address bits produced by the address counter (11) and a lower address decoder (14) decodes the lower valued bits.