发明名称 MULTI-PROCESSOR SYSTEM
摘要 PURPOSE:To simplify the processing of a fault in a multi-processor system, by constituting so that the processor concerned can be set forcibly to a mode of a faulty state, when an abnormal state of other processor is detected. CONSTITUTION:In case when a processor 1 executes an inter-device communication to a processor 2 and 3, the processor 1 sends out a transmitting signal to the processor 2 and 3, and thereafter, waits for its response for a constant interval of time. In case when no response is received from the processor 2, the processor 1 can decide that the processor 2 is not in a normal state. In that case, when the processor 1 sets a faulty state requesting circuit 132, a faulty state displaying circuit 21 is set, and the processor 2 is set to a mode of a faulty state. By an output of this circuit 21, faulty state displaying circuits 122, 322 are set, and the fault processing is started. In this way, the processors 1, 3 can detect the faulty state of the processor 2 in the same way as the faulty state of its own device, therefore, the processing of a fault can be simplified.
申请公布号 JPS58211268(A) 申请公布日期 1983.12.08
申请号 JP19820094065 申请日期 1982.06.03
申请人 NIPPON DENKI KK 发明人 MAEKAWA KAZUHIKO
分类号 G06F11/18;G06F11/00;G06F15/16;G06F15/177 主分类号 G06F11/18
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