| 摘要 |
In order to optimise the ramp rate of the h.v. supply in EEPROM and other charge storage supplies whilst not dissipating power nor loading the substrate bias generator, the ramp voltage V0 from a voltage multiplier (Figure 3) is applied to a regulating transistor T1 channel. The gate of the transistor is capacitively coupled to the ramp voltage terminal, and is connected to supply VS via constant current sink T2. If the ramp at V0 is too slow, T1 turns off, removing any current drain from the voltage multiplier. If the ramp is too fast, the capacitor couples a higher current than I1 to node V1, turning transistor T1 on more, and thus decreasing the ramp rate. T1 sinks current to earth rather than the substrate. <IMAGE> |
