| 摘要 |
PURPOSE:To realize a scan in/scan out testing system through less external terminals without any resriction, by applying a rectangular wave signal with prescribed time width to the initial stage of a gate selecting circuit during a test. CONSTITUTION:The gate selecting circuit 23 consists of delay elements having a delay time longer than the time necessary for observing output states of logical elements in a logical circuit device body 21 and the time taup necessary for setting test data in a latch circuit in the device body 21, and a pulse with the pulse width taup is applied to the initial-stage delay element to perform scan in/ scan out operation successively by outputs of respective stages of the delay element. Consequently, the number of external terminals is decreased greatly as compared with that of a device provided with an address decoding circuit and the scan in/scan out testing system is realized without any restriction. |
