发明名称 Three level poly dynamic ram with poly bit lines
摘要 First polycrystalline silicon layers are insulatively disposed over a p-type semiconductor substrate. Second polycrystalline silicon layers are formed on the substrate adjacent to the first polycrystalline silicon layers. Third polycrystalline silicon layers are insulatively disposed over the substrate between the first polycrystalline silicon layers and the second polycrystalline silicon layers. The third polycrystalline silicon layers function as gates of MOS transistors, and the first polycrystalline silicon layers function as capacitors in cooperation with the substrate. The second polycrystalline silicon layers function as the digit lines, and are so formed as to alternately contact substrate and pass over the first polycrystalline silicon layers insulated therefrom by thick insulative layers.
申请公布号 US4419682(A) 申请公布日期 1983.12.06
申请号 US19810227936 申请日期 1981.01.23
申请人 TOKYO SHIBAURA DENKI KABUSHIKI KAISHA 发明人 MASUOKA, FUJIO
分类号 G11C5/02;G11C11/404;H01L23/522;H01L27/108;(IPC1-7):H01L27/10;H01L23/50;G11C11/40 主分类号 G11C5/02
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