| 摘要 |
<p>PURPOSE:To attain modulation and demodulation of a digital data signal easily, by providing a word synchronous signal having a pulse width being >=1.5 times of a bit period at each word and a parity data of at least one-bit. CONSTITUTION:The word synchronous signal having a pulse width being >=1.5 times the bit period T, by inhibiting the inversion at two edge positions of bits within two-bit range of the word synchronous signal part S. As to the parity data, the selection is done so that ''Os'' are an even number including the 2-bit data of the part S. The data is fixed depending whether the polarity of the front edge of the start of each word goes upward or downward, by selecting even number of data ''Os'' in one-word. Thus, the modulation/demodulation of the digital data signal is done easily, the circuit constitution is simple and the polarity of the word synchronous signal is unchanged, allowing to attain high timing accuracy of the edge (arrow) for reference phase determination.</p> |
