MEMORY CIRCUIT

摘要

A read resettable memory circuit contains a flip-flop circuit (10) consisting of a flip-flop (FF) and an edge-triggered control circuit (CC) and a fall-through latch (16). The control circuit sets the flip-flop in response to a selected edge transition in a first clock (O1) when an appropriate external logical set signal (S) is received and resets the flip-flop in response to a selected edge transition in a second clock (O2) when an appropriate feedback logical reset signal (R) is received. The latch provides the reset signal at a value corresponding to the current logic state of the flip-flop during each period running from the selected edge transition of the second clock to its opposite edge transition and at a value corresponding to the logic state of the flip-flop that exists just before each opposite edge transition of the second clock during each remaining following period.