| 摘要 |
PURPOSE:To correct the fluctuation of an output waveform due to dispersion in a manufacturing stage by constituting a well region of a gate circuit of CMOS transistor (TR) circuits of series connection of plural stages so as to be controlled from the outside as intervals of odd number. CONSTITUTION:P channel CHMOS TRs Q1-Q3 are formed on an N<-> substrate, and the potential of the substrate is made to a potential equal to a power supply VDD. NCHMOSTRs Q4-Q6 are formed on a P well region provided at a part on the N<-> substrate and the potential of the substrate is made to equal to the ground. TRs Q1 and Q4, Q2 and Q5, and Q3 and Q6 constitute the CMOS inverters, respectively and the P well region of the TRs Q4, Q6 of the 1st and the 3rd stages is connected to a control terminal 13 controlling the potential of the region. In changing the potential at a terminal 13, the threshold value level of the inverter of the 1st and the 3rd stages is changed and the fetching level of the signal applied to the 1st and the 3rd stages is changed, then the propagation delay time from an input terminal 11 to a terminal 12 and a waveform at the terminal 12 are changed, allowing to correct the fluctuation due to the dispersion in the manufacturing stage. |
