| 摘要 |
PURPOSE:To reduce the degree of effect due to crosstalk noise and over-write noise, by performing write with a different phase from those of adjacent cylinders and written information before duplicated write. CONSTITUTION:The titled circuit contains a delay circuit 1, a logical inverter 2, AND circuits 3, 4 and an OR circuit 5, and they are connected in such a way that two input terminals of the AND circuit 3 are connected to an input terminal of the delay circuit 1 and an input terminal of the logical inverter 2 respectively, two input terminals of the AND circuit 4 are connected to an output terminal of the delay circuit and an output terminal of the logical inverter 2 respectively, and two input terminals of the OR circuit 5 are connected to an output terminal of the AND circuit 3 and the output terminal of the AND circuit 4 respectively. In this way, write information (g) written in the same address is switched for a signal (a) and a signal (b) at each write and the information having different phase is obtained. Thus, the degree of effect due to crosstalk noise and over-write noise is reduced. |
