| 摘要 |
PURPOSE:To reduce the power consumption and furthermore to minaturize the chip size for integration, by arraying plural MOS electrodes in roder to form a staircase type potential well on the surface or at the inside of a semiconductor substrate and applying voltages of different levels to these MOS electrodes for formation of said potential well. CONSTITUTION:Plural resistances 30A, 30B, 30C... are formed with n type impurity regions 51A, 51B, 51C... of low concentration which are formed within a p type semiconductor. A fixed voltage is divided by a voltage dividing circuit 31 consisting of resistances 30A, 30B, 30C... of extremely high resistance factors. These divided voltages are applied to gate electrodes 25A, 26A, 25B, 26B... to form a staircase potential well. Then the electric charge is stored in this potential well. |
