发明名称 CLOCK PULSE GENERATING CIRCUIT
摘要 <p>PURPOSE:To assure the start of oscillation, by combining two monostable multivibrator elements of a CMOSIC to obtain an AND of the negative logic output of these elements and using this AND as the pull-up potential of an external resistance for decision of pulse width of one of both elements. CONSTITUTION:If the 1st and 2nd monostable multivibrators 1 and 2 are stabilized when a power supply is applied, the output Q is set at H with its AND set at L as shown in figures (a) and (b). The potential of a connection terminal 4 drops as shown in the figure (c). When the potential of the terminal 4 drops less than the threshold level, the output Q of the vibrator 1 is inverted to L. Therefore, the output of an AND gate 5 is set at H, and the potential of the terminal 4 rises up and exceeds again the threshold level. As a result, the output Q of the vibrator 2 is set at H and then inverted to L to trigger the vibrator 1. Thus a clock pulse generating circuit starts its oscillation. When the oscillation is once started, the input of the gate 5 is alternately set at L. While the output of the gate 5 is always set at H.</p>
申请公布号 JPS58206225(A) 申请公布日期 1983.12.01
申请号 JP19820090094 申请日期 1982.05.27
申请人 NIPPON DENKI KK 发明人 YOKOGAWA TAKASHI
分类号 H03K3/03;G06F1/04;H03K3/014 主分类号 H03K3/03
代理机构 代理人
主权项
地址