发明名称 SCAN TEST METHOD FOR LSI BUILT-IN MEMORY
摘要 PURPOSE:To perform efficiently a test by plural patterns in the same input pattern, by selecting each bit which paralleling both positive and negative signals of one word scanned-in to an input register. CONSTITUTION:A specified one word test pattern is stored in an input register forming a shift register with a scan-in signal, and a register 1 outputs a positive and negative signals in parallel for each bit. One of the parallel outputs is selected by a multiplexer 2 according to a selection signal and supplied to an LSI built-in memory 3 and a comparator 5. The comparator 5 compares the read out output of the memory 3 to test the quality of the memory 3. As the result, the test of the LSI built-in memory is efficiently performed by the test of various patterns based on the same test pattern with one time the scan-in.
申请公布号 JPS58205993(A) 申请公布日期 1983.12.01
申请号 JP19820088272 申请日期 1982.05.25
申请人 FUJITSU KK 发明人 HASHIGUCHI KOUJI
分类号 G06F12/16;G01R31/3185;G11C29/00;G11C29/02;G11C29/08;G11C29/56;H01L21/66;H01L21/822;H01L27/04;H01L27/10 主分类号 G06F12/16
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