| 摘要 |
A TTL MOS clock converter for converting a low-amplitude clock signal with a signal level which is different from the operating voltage into a large-amplitude clock signal with a level equal to the operating voltage, has a TTL input inverter (ST1), a reset clock stage (ST2, ST3, ST4) with three inverters and one power stage (SS, D, E) which, in turn, consists of a switching stage (SS), a delay stage (DD) with two inverters and an output stage (E) also with two inverters. Reset clock stage (ST2, ST3, ST4) and power stage (SS, D, E) are directly activated by the input inverter stage (ST1); the reset clock stage (ST2, ST3, ST4) supplies two reset signals (rsh, rsl) to the power stage (SS, D, E). <IMAGE>
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