| 摘要 |
PURPOSE:To take in asynchronous signals at high speed by making a microprocessor in the state of data transfer completion recognition artificially using the second clock signal of advanced phase. CONSTITUTION:A data transfer completion signal, the inverse of DTACK1 supplied to a microprocessor by estimated starting synchronizing with trailing edge of a preceding clock signal OSC is made active and after 1/4 period, the microprocessor MPU makes recognition synchronizing with the clock signal CLK. Thereafter, before timing when a clock signal OSC changes to low level, at the latest, if a true data transfer completion signal, the inverse of DTACK0 is made active of low level, the microprocessor MPU takes in data synchronizing with the change of next clock signal CLK to low level. Thus, taking in of data is completed after delay time of about 1/4 period from low level of the true data transfer completion signal, the inverse of DTACK0 in the case of shortest time. |
