发明名称 POWER MANAGEMENT APPARATUS AND METHOD
摘要 A computer system is provided for monitoring the activity of a bus controller (208) of a processor (204) and responsive thereto for controlling the power consumption of a target controller such as memory controller (216) coupled to the bus controller (208). The computer system includes a bus (202), a processor (204), and a bus activity monitor (212) for generating a bus activity signal indicative of activity in the bus controller (208). The target controller (memory controller (216)) controls the exchange of information between the processor (204) and a target circuit such as DRAM (218). The target controller (216) has an input (215) for receiving a sequencing signal. The computer system additionally includes a power management circuit (220) for controlling the power consumption of the target controller (216). The power management circuit (220) receives the bus activity signal and generates the sequencing signal in response to the bus activity signal.
申请公布号 WO9724653(A1) 申请公布日期 1997.07.10
申请号 WO1996US20807 申请日期 1996.12.27
申请人 INTEL CORPORATION;KARDACH, JAMES, P.;CHUNG, CHIH-HUNG;ZILLER, JASON 发明人 KARDACH, JAMES, P.;CHUNG, CHIH-HUNG;ZILLER, JASON
分类号 G06F1/32;(IPC1-7):G06F1/32 主分类号 G06F1/32
代理机构 代理人
主权项
地址