| 摘要 |
1382082 Semi-conductor devices PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 14 March 1972 [17 March 1971] 11771/72 Heading H1K The under-etching of a lower masking layer 22, Fig. 2f, beneath a portion 29 of an upper masking layer 21 around a small aperture 23 in the upper masking layer 21 through which the etching is carried out is employed in semiconductor device manufacture to differentiate, with only a single photomasking process, two surface regions 18a, 20 of the semi-conductor body in which different selective treatments are to be effected. Both selective treatments may involve dopant introduction by diffusion or ion implantation, but Fig. 2h illustrates a method in which the smaller surface region is subjected to dopant introduction while the larger surface region is selectively oxidized to produce an inset oxide layer 26. During this oxidation the previously introduced dopant diffuses further into the semi-conductor body to form a region 27 beneath the oxide 26. In the embodiment shown the regions 26 and 27 combine to form a lateral isolation wall around an island 7 of an integrated circuit structure. The island 7 contains a bipolar transistor the base 3 and emitter 2 of which may optionally extend laterally to intersect the inset oxide 16. Several variations of the Fig. 2h structure are disclosed. Thus, for example, whereas in Fig. 2h the oxide 26 only extends partly through an N type epitaxial layer 5 on P-type substrate 6, Fig. 3a (not shown), illustrates a situation in which the inset oxide (126) extends fully through the epitaxial layer (5) and the P<SP>+</SP> region (127) beneath the oxide extends into the P-type substrate (6) to form a channel-interrupting zone. The additional depth of oxide (126) may be achieved merely by oxidizing for a longer period or by initially oxidizing partly through the layer (5), etching out the oxide so formed, and finally oxidizing again within the recess thus provided. The intial oxidation step may also be dispersed with and replaced by a straightforward etching process extending partly through the epitaxial layer (5). In this case the inset oxide may have its upper surface level with that of the epitaxial layer. A preliminary oxidation through the small aperture alone may also be carried out. The channel-interrupting function of the region diffused through the small aperture and finishing beneath the inset oxide layer may be employed in the target of a camera tube or in an integrated circuit comprising a plurality of I.G.F.E.T.s. Fig. 9a illustrates an embodiment in which regions 96, 97 underlying inset oxide layers 113, 98 comprise source and drain regions of an I.G.F.E.T. The situation of the drain region 97 entirely within the boundary of the inset oxide 98 produces an offset-gate device, since the gate electrode 103 is effectively laterally spaced from the drain region 97. A variety of devices are described in which both of the regions subjected to selective treatment contain diffused impurities. Fig. 12a shows a bi-polar transistor of which the emitter region 193 is diffused through the small aperture, the base region is diffused through the underetched aperture in the lower masking layer, and an extension 192 of the base region, to which the base contact 197. is applied, is diffused through an aperture sufficiently close to the underetched aperture for the two regions to merge as shown. Numerous detailed variations on the above-described embodiments are also disclosed. The two masking layers 21, 22 (Fig. 2f) may be of silica oxide and silicon nitride, applied in either order. Aluminium oxide, silicon carbide or polycrystalline silica may also be used as masking materials. The overlapping portion of the upper masking layer 21 may be removed by ultrasonic vibration during the etching of the large aperture 24 in the lower masking layer 22, or may be removed subsequently by etching away half the thickness of the upper layer 21, the overlapping portion 29 being attacked on both its upper and lower surfaces. |
