| 摘要 |
The digital synchronization circuit produces multiple clock signals delayed a predetermined amount from an independent clock's signal. When it is desired to synchronize a signal, the digital synchronization circuit determines the optical clock signal to synchronize to and produces a signal synchronized to that clock signal. A delay line is connected to the independent clock signal to produce said multiple clock signals. A digital logic device is connected to the delay line. In response to a trigger signal indicating that synchronization is desired, the digital logic device selects one of the multiple clock signals as the optimal clock signal and produces a signal synchronized to the selected clock signal. The digital logic is also supplied with inverted versions of said multiple clock signals and comprises logic AND gates and logic OR gates.
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