| 摘要 |
PURPOSE:To allow variance of address decoders and data buffers, by realizing high-speed data transfer between an input and an output port in every successive clock period. CONSTITUTION:A signal BSS indicating the address of a port 320 is supplied to the BSS decoder 340 of a unit 30-0 in synchronization with a system clock CLK and when a signal SEL rises, the input port 320 of the unit 30-0 is energized to send data DATA latched therein out to a bus 40. A signal BDS indicating the address of a port 1 is inputted to the BDS decoder 342 of a unit 30-1 in the same period of the clock CLK. When the signal SEL falls and a leading edge of a latch signal LCH arrives, an output port 322 is energized to latch data on the bus 40, i.e. data DATA transferred from the port as effective data at the port. |
