发明名称 Dynamischer RAM mit Spannungsstressanlegeschaltung
摘要 A dynamic random access memory comprising a dynamic memory section (15), a first screening-test pad (24), a second screening-test pad (25), and a mode-setting circuit (31). The dynamic memory section includes a memory-cell array (15) having dynamic-type memory cells (MC) arranged in rows and columns, a row circuit and a column circuit, both connected to the memory-cell array, and a refresh counter (12) for generating a refresh address signal for refreshing the dynamic-type memory cells when the dynamic memory section is set in a CBR refresh mode. The first screening-test pad (24) receives a first external control signal for setting the dynamic memory section in an ordinary mode or a screening-test mode. The second screening-test pad (25) receives a second external control signal for setting the dynamic memory section in the CBR refresh mode. The mode-setting circuit (31) detects whether or not the first control signal and the second external control signal are in predetermined states, and enables the row circuit and the column circuit upon detecting that the first and second control signals are in the predetermined states, thereby to cause the refresh counter to supply the refresh address signal to the row circuit and the column circuit. <IMAGE>
申请公布号 DE69317964(T2) 申请公布日期 1998.09.10
申请号 DE1993617964T 申请日期 1993.08.31
申请人 KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP;TOSHIBA MICRO-ELECTRONICS CORP., KAWASAKI, JP 发明人 OGIHARA, MASAKI, C/O INTELLECTUAL PROP. DIV., MINATO-KU, TOKYO 105, JP
分类号 G11C11/407;G01R31/317;G11C11/401;G11C11/403;G11C11/406;G11C29/00;G11C29/06;G11C29/14;(IPC1-7):G11C29/00;G06F11/26 主分类号 G11C11/407
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