发明名称 DELAY CIRCUIT
摘要 <p>PURPOSE:To obtain stably a delay time longer than the transfer time of a transistor (TR) by causing a current being the division of a constant current of a constant current source in a prescribed ratio according to the current mirror ratio to flow to a capacitor. CONSTITUTION:An input PNP TR Q4 of a current mirror circuit 10 and a constant current source circuit 11 are connected in series between an emitter of a switch TR Q1 and ground, and one terminal of the said capacitor C and a base of a TR Q2 of a voltage comparison circuit 1 are connected to a collector of an output PNP TR Q5 of a current mirror circuit 10. It is possible to decide a delay time the from the inversion of a switch input signal till the inversion of comparison output depending on the quantity of the charging current of the capacitor C, and since the charging current is set to a minute current by the current mirror circuit 10, the long delay time td is obtained.</p>
申请公布号 JPS62200815(A) 申请公布日期 1987.09.04
申请号 JP19860042901 申请日期 1986.02.28
申请人 TOSHIBA CORP 发明人 MIZUIDE YASUO
分类号 H03K5/13 主分类号 H03K5/13
代理机构 代理人
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