发明名称 DIGITAL FILTER CIRCUIT
摘要 PURPOSE:To set the primary delay constant at 0-infinity , by using a digital filter. CONSTITUTION:A subtractor 1 performs a subtraction between the i-th input Xi and Yi-1 supplied from a storage device 4. A constant multiplier 2 performs (alpha) multiplication of the output (Xi-Yi-1) of the subtractor 1 by the set numerical value. An adder 3 performs an addition of the output alpha(Xi-Yi-1) of the multiplier 2 and the output Yi-1 of the device 4 and delivers Yi-1+alpha(Xi-Yi-1). The device 4 stores the output of the adder 3 and then delivers this output at the next operation. This output means that an operation Yi=Yi-1+alpha(Xi-Yi-1) is carried out for an output signal X to obtain a filter effect. Therefore, it is possible to set the primary delay time constant at 0-infinity by varying the filter coefficient alpha in a range 0-1.
申请公布号 JPS58202620(A) 申请公布日期 1983.11.25
申请号 JP19820085931 申请日期 1982.05.21
申请人 MITSUBISHI JUKOGYO KK 发明人 TOUJIYOU TAKAO
分类号 H03H17/04;(IPC1-7):03H17/04 主分类号 H03H17/04
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