| 摘要 |
<p>An image processing apparatus which can reduce the power consumption by a large extent, wherein a predetermined shape to be displayed on a display is expressed by a composite of unit graphics by performing operations on a plurality of pixels simultaneously and by performing processing on valid results of operations for pixels positioned inside a unit graphic being processed. Clock enablers (2101 to 2151, ... 2108 to 2158) in operation sub-blocks (2001 to 2051, ... 2008 to 2058) judge the validity of the corresponding val data (S2201, ..., S2208). Only operation sub-blocks receiving the corresponding val data indicating validity perform operations. Other operation sub-blocks do not perform operations. The operation blocks (200 to 205) perform pipeline processing. <IMAGE></p> |
