Computer system comprising a data, address and control signal bus which comprises a left bus and a right bus.

摘要

A computer system comprises a bus for data, address and control signals which is divided into a left bus (36) and a right bus (38) by a first gating device (34). The gating device has an open state which is character-wise activated by a right bus request transported on the left bus. Furthermore, the gating device conducts start signals from a processor station (28) connected to the left bus and interrupt signals from a peripheral apparatus connected to the right bus. In the closed state of the gating device, bulk data transport is possible on the right bus without interfering with the processor station. The processing speed is thus increased.