发明名称 TESTING DEVICE OF INTEGRATED CIRCUIT
摘要 PURPOSE:To obtain logical indiscrete values ''1'' and ''0'' of the output signal of an integrated circuit to be tested with only one starting of a test pattern sequence, by providing a circuit for holding maximum and minimum voltage values of the output signal and its scanner in an output signal detecting circuit. CONSTITUTION:A block 7 is a minimum voltage holding circuit and detects the minimum value of logical analog level ''1'' of the output of the integrated circuit (DUT) to be tested, which is inputted through an analog switch 9, for every one pattern, and the minimum value is updated successively and is held. A block 8 is a maximum voltage holding circuit and detects the maximum value of logical analog level ''0'' of the output of the DUT, which is inputted through an analog switch 10, for every one pattern, and the maximum value is updated successively and is held. Thus, it is discriminated that the output signal performs a correct logical operation if the discrimination result of a block 4 is PASS by starting the test pattern sequence only once, and held voltages of blocks 7 and 8 indicate minimum and maximum voltages of logical ''1'' and ''0'' of the output pin on this DUT.
申请公布号 JPS58201079(A) 申请公布日期 1983.11.22
申请号 JP19820084336 申请日期 1982.05.19
申请人 NIPPON DENKI KK 发明人 EGUCHI YASUO
分类号 G01R31/28;G01R31/317;G01R31/319 主分类号 G01R31/28
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