| 摘要 |
PURPOSE:To improve the working ratio of a CPU and to relieve the software load, by giving a suitable set value to a reload register and a circuit counter from the CPU and outputting a signal having a desired period and the number of pulses automatically. CONSTITUTION:An output signal from the CPU1 is given to a decoder 2, and its decoding signal loads a set value to a reload register 3 and sets and resets an FF6. An output of this register 3 sets a timer conunter 7 to the set value. On the other hand, a counter 4 counting the number of times comprising down- couters counts down the output pulse number of the counter 7 and when the counter 7 reaches zero, an output Qc goes to a high potential to set the FF6. Further, the counter 7 counts down a clock signal CLK from the set value, and when it reaches zero, a pulse signal Qt is outputted. The logical product between this signal Qt and an output Q1 of the FF6 is outputted from an FF11 via a logical circuit through the counter 7. |
