| 摘要 |
A phase shift binary modulator which is less sensitive to the non-linear characteristics of the transmission channel. The modulator comprises a first input to which a succession of binary bits are applied, prior to their modulation and transmission. Another input receives a clock signal at the bit rate of the succession of bits applied to the first input terminal, which is, in turn, connected to an input of a first exclusive OR gate, the output of which is connected to an input of another exclusive OR gate. The output of the other OR gate is connected to the input of a flip-flop. An output of the flip-flop is connected to the second input of the first OR gate. The clock signal drives a divider, the inverse output of which is connected to the second input of the other OR gate. The direct output of the divider is connected to an input of an AND gate. The second input of the AND gate is connected to the output of a delay circuit. The binary modulator may have either four or eight phase-shift displacements. In the four shift embodiment the binary symbol "1" is transmitted by a phase shift of + pi /2, and the binary symbol "0" is transmitted by the phase-shift of - pi /2. In the eight shift embodiment, the binary symbol "1" is transmitted by two successive shifts of + pi /4, and the binary symbol "0" is transmitted by two successive shifts of - pi /4. The successive shifts of + or - pi /4 are performed at a clock rate which is double the numerical rate of delivery of the modulating binary signal.
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