发明名称 SYNTHESIZER SYSTEM SUPERHETERODYNE RECEIVER
摘要 PURPOSE:To attain the reception without tracking error, by providing a phase locked loop for receiving tuning circuit having another voltage controlled oscillator generating a signal having the same frequency as a receving frequency of a receiver in addition to a phase locked loop for local oscillation. CONSTITUTION:The phase locked loop PLL14 is provided for local oscillation and the PLL20 for receiving tuning circuit is provided additionally. This PLL20 frequency-divides an output signal from the voltage controlled oscillator VCO' 201 at a programmable frequency divider 202 in the frequency dividing ratio based on an external receiving frequency data. Then, the oscillating frequency obtained from the oscillator VCO'201 is the signal having the same frequency as the receiving frequency of the receiver. Further, an inductance L1 of a high frequency amplifier 12 and an inductance L2 of the oscillator VCO'201 are made as equal inductance and varactor diodes D1, D3 used for the amplifier 12 and the oscillator VCO'201 are those of well arranged characteristics, allowing the oscillator VCO'201 to be oscillated in the same frequency as the receiving frequency of the receiver.
申请公布号 JPS58200635(A) 申请公布日期 1983.11.22
申请号 JP19820084164 申请日期 1982.05.19
申请人 NIPPON VICTOR KK 发明人 KANEZASHI HISASHI;SANO SHIYOUJI;YAKO SATORU
分类号 H04B1/26;H03J5/02 主分类号 H04B1/26
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