发明名称 MASTER-SLICE SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To obtain the master-slice LSI, in which cells, density thereof is high and performance thereof is also high, are arranged in a two element shape, by disposing a contact position of the gate of a transistor so as to extremely avoid the use of buried wiring. CONSTITUTION:The positional relationship of a pair of contacts S1, M1 to the gate wiring of a P type transistor P and an N type transistor N forming a pair is reversed to the positional relationship of another contact pair S2, M2. A layout pattern of the wiring of one part of a flip-flop circuit with a reset is shown in the figure. A pattern in which oblique lines rising to the right are formed represents signal line wiring, and a pattern in which oblique lines falling to the right are formed represents a power supply line. P Type source-drain 41 constituting a pair of a TG1 and a TG2 are connected directly by Al, and buried wiring (E1-F1) need not be used excessively.
申请公布号 JPS58200556(A) 申请公布日期 1983.11.22
申请号 JP19820083476 申请日期 1982.05.18
申请人 NIPPON DENKI KK 发明人 MIZUMURA HISASHI
分类号 H01L27/092;H01L21/82;H01L21/8238;H01L27/118 主分类号 H01L27/092
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