| 摘要 |
In an asynchronous transmission mode, the bit synchronization arrangement receives data signals in the form of binary pulse trains (at A). It includes an oscillator (3) whose output signal (at C) has a frequency FOS approximately equal to twice the binary rate of the pulse trains and a transition detector (1, 22) which supplies a calibrated voltage pulse (at B2) at each data signal transition. The oscillator supplies a triangular internal signal (at D) at the frequency FOS and a phase correction circuit (2) is provided to reduce the algebraic value of the slope of this signal during each calibrated pulse so as to produce a predetermined constant advancing or delaying phase shift according as the calibrated pulse occurs during a negative or a positive ramp of this signal. |
