| 摘要 |
<p>A clock recovery circuit capable of outputting decision point data without causing any slip of a recovered clock in the case of operation in a continuous mode in a demodulator in which received signals are sampled by a fixed frequency clock to obtain the recovered clock and symbol data are demodulated by using this recovered clock. This circuit comprises: non-linear processing means (4029 for carrying out a non-linear processing of an analog-digital-converted quasi-coherent detection received signal; first multiplying means (423, 424) for multiplying each of COS/-SIN values (+/-1. 0) oversampled with a frequency of 4 times to the non-linearly processed signal; means (425, 426) for averaging multiplied results obtained in the first multiplying means; second multiplying means (427, 428) for multiplying each of COS/-SIN values (+/-1, 0) oversampled with a frequency of 4 times to an averaged result obtained in the averaging means; and addition means (429) for summing multiplied results obtained in the second multiplying means. <IMAGE></p> |
