| 摘要 |
PURPOSE:To specify both an odd and an even number to be used for an address whose coincidence should be detected, by controlling the least significant digit bit of an address to be inputted to a comparator from a processor. CONSTITUTION:An address output circuit 5 detects the processor 1 goes to data transfer mode by a control signal from a control bus 1c. When the transfer mode is detected, the least significant least significant digit bit is held high or low and outputted to the comparator 4. The comparator 4 inputs an address other than the least significatnt digit bit from an address bus 1b and the output address Aoc from the circuit 5 to make a comparison with the output of a latch circuit 3. The circuit 5 detects an address Ao and a control signal -BHE and divides one bus cycle into the former and latter half parts for high and low addresses, outputting the address Ao to the comparator 4. Therefore, even when an even-numbered address word transfer address is outputted from the processor 1, the comparator 4 is supplied with an odd or even set address. |
