发明名称 LOGICAL CIRCUIT SIMULATING METHOD
摘要 PURPOSE:To shorten considerably the computer processing time required for circuit simulation, by extracting only a basic circuit which performs output signal calculation in an equivalent logical circuit and performing the simulation. CONSTITUTION:Control bits CF1 and CF2 are used for all basic circuits 14, 15, and 16 of the equivalent logical circuit 10. If the output value of some basic circuit varies, the CF1 is off when signal variation is 0 or on when 1. The CF2, on the other hand, means that an output signal is not ransferred to a connection destination by 0 and that the signal is transferred by 1. The CF1 and CF2 are all set to 0. Then, the CF1 and CF2 of the circuit 14 of a test signal line 12 are set to 1 firstly and the bits CF2 of the circuits 16 and 17 are set to 1 next; and this procedure is repeated until an application node. The circuit simulation is started and output signal values of only the circuits 16, 17, and 14 whose bits CF2 are set to 1 are calculated, testing the output signal value of the circuit 14 logically.
申请公布号 JPS58200353(A) 申请公布日期 1983.11.21
申请号 JP19820083022 申请日期 1982.05.19
申请人 HITACHI SEISAKUSHO KK 发明人 TSURUMI EIICHI;MIYOSHI MASAYUKI
分类号 G06F11/25;G06F17/50 主分类号 G06F11/25
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