| 摘要 |
PURPOSE:To perform high-speed operation by performing clock control over a transfer gate and the gate of a specific MOS transistor (TR). CONSTITUTION:Buses 1 and 2 are connected to an interface 3. It is assumed that a larger load is connected to the bus 1 than the load connected to the bus 2. The interface 3 consists of CMOSTRs; P channel TRs 4 and 5 and N channel TRs 6 and 7 are connected in series. The bus 2 is connected to the gates of the TRs 5 and 6 and the bus 1 is connected to the output of a CMOS inverter; the buses 1 and 2 are connected to each other through the transfer gate 8. The transfer gate 8 and the gates of the TRs 4 and 7 are connected to the outputs of OR gates 9 and 10, which input the negative-phase clock phi' of a clock phi. Thus, high-speed operation is carried out. |
