发明名称 INPUT AND OUTPUT PROCESSOR
摘要 PURPOSE:To connect and control plural high-speed input and output devices which have nearly equal data transfer capability, by providing a data transfer controlling part with an FF for detecting the priority of data transfer. CONSTITUTION:An input and output processor is provided with a microprocessor 1, storage part 2, plural input and output connection parts 4 and 5, plural input and output device parts 6 and 7, and data transfer controlling part 3. The storage part 2 consists of memory elements in and out which data is written and read. The input and output device parts 6 and 7 operate at high speeds respectively and has nearly equal data transfer capability. The data transfer controlling part 3 has a priority deciding circuit provided with the FF10 for determining the priority of data transfer to control the data transfer between the storage part 2 and input and output device parts 6 and 7 through the input and output device connecting parts 4 and 5.
申请公布号 JPS58200323(A) 申请公布日期 1983.11.21
申请号 JP19820082268 申请日期 1982.05.14
申请人 NIPPON DENKI KK 发明人 AKIMOTO KENJI
分类号 G06F13/362;G06F13/18 主分类号 G06F13/362
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