| 摘要 |
An array processor consisting of a plurality of sections (S1, S2-S9), with switching means (24,26,30,32) selectively operable to by-pass any one of the sections so as to effectively remove it from the system. One of the sections normally acts as a stand-by, and is by-passed. However, if one of the other sections fails, that section is by-passed and the stand-by is returned to service. The currently active sections are allocated sequential addresses.
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