| 摘要 |
<p>PURPOSE:To control in parallel an operation of other independent operating system without exerting no influence on the operating system by a fundamental clock operation, by effectively using a fixed storage part in a system. CONSTITUTION:A fundamental clock C0 from a clock generator 100 is supplied to an address counter 103 and also is supplied to an AND gate 105. The address counter 103 generates ROM addresses A0-A3 of 4 bits by synchronizing with this fundamental clock C0. These ROM addresses A0-A3 are supplied to an ROM104, and contents of an address following its input address are read out as output data B0-B3 from the ROM104. Among the output data of this ROM104, the data B0-B2 of 3 bits are supplied to a logic part 101, and the data of B3 bit is supplied to the AND gate 105 and a refresh control circuit 106.</p> |
