| 摘要 |
PURPOSE:To eliminate the disturbance of a pipeline control due to branch instruction to process branch instructions in a high speed, by obtaining branch addresses of branch instructions to read branch destination instructions from an instruction private memory. CONSTITUTION:An instruction group read out from an instruction private cache memory 2 is stored in a buffer register 4. Before this storage, an instruction arranging circuit 5 arranges respective instructions to read out the instruction group from the memory 2. An instruction decoding circuit 16 decodes instructions of the output from the circuit 5. When a branch instruction is decoded, an update monitor circuit 17 detects whether a register, which generates the branch address of the branch instruction, is updated before the execution of the branch instruction by a preceding instruction or not. If it is detected that this register is not updated, a branch address calculating circuit 18 obtains the branch address of the branch instruction to make it possible to prefetch the branch destination instruction. |
