| 摘要 |
PURPOSE:To attain a data separating circuit in which the margin of a setup time of data in latch input is large and no phase adjustment is required. CONSTITUTION:An enable pulse phi1 and a clock pulse CA are inputted to a latch circuit 25 and an output as shown in a figure 6 is obtained, a pulse phi2 and the clock pulse CA are inputted to a latch circuit 28 and an output (b) is obtained. A latch circuit 26 latches the output of the latch circuit 25 with the pulse phi2 and the CA. The timing of the output is shown in a figure 7. Latch circuits 27, 29 are operated with a clock pulse CB and the pulse phi2. When the pulse CB is inputted to an input terminal 23, the timing of the latch circuits 27, 29 is as shown in figures 10, 11. As mentioned above, it is used that the period of the change in the output data is double that of the pulse CB, and the setup time of data at the input of the latch circuits 27, 29 is increased more than that of conventional circuits. |
